R5F5651EDDFM datasheet(123/188 Pages) RENESAS

123 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 123 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.6

EXDMAC Timing

Figure 2.30

EDREQ0 and EDREQ1 Input Timing

Figure 2.31

EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)

Table 2.26

EXDMAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

ICLK = PCLKA = 8 to 120 MHz, PCLKB = BCLK = SDCLK = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

EXDMAC

EDREQ setup time

tEDRQS

—

Figure 2.30

EDREQ hold time

tEDRQH

2—

EDACK delay time

tEDACD

—

Figure 2.31,

Figure 2.32

BCLK pin

tEDRQS tEDRQH

EDREQ0,

EDREQ1

EDACK0,

EDACK1

tEDACD

BCLK pin

tEDACD

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