R5F5651EDDFM datasheet(126/188 Pages) RENESAS

126 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 126 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.2

TPU

Note 1. tPBcyc: PCLKB cycle

Figure 2.34

TPU Input Capture Input Timing

Figure 2.35

TPU Clock Input Timing

Table 2.28

TPU Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

TPU

Input capture input pulse

width

Single-edge

setting

tTICW

1.5

—

tPBcyc

Figure 2.34

Both-edge

setting

2.5

—

Timer clock pulse width

Single-edge

setting

tTCKWH,

tTCKWL

1.5

—

tPBcyc

Figure 2.35

Both-edge

setting

2.5

—

Phase counting

mode

2.5

—

Input capture

input

PCLKB

tTICW

TCLKA to

TCLKD

PCLKB

tTCKWL

tTCKWH

R5F5651EDDFM Datasheet(PDF) 126 Page - Renesas Technology Corp

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