R5F5651EDDFM datasheet(132/188 Pages) RENESAS

132 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 132 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.7

A/D Converter Trigger

Note 1. tPBcyc: PCLKB cycle

Figure 2.45

A/D Converter Trigger Input Timing

2.4.7.8

CAC

Note 1. tPBcyc: PCLKB cycle

Note 2. tcac: CAC count clock source cycle

Table 2.33

A/D Converter Trigger Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

A/D

converter

A/D converter trigger input pulse width

tTRGW

1.5

—

tPBcyc

Figure 2.45

Table 2.34

CAC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item*1, *2

Symbol

Min.*1, *2

Max.

Unit

Test

Conditions

CAC

CACREF input pulse width

tPBcyc ≤ tcac

tCACREF

4.5 tcac +

3 tPBcyc

—ns

tPBcyc > tcac

5 tcac +

6.5 tPBcyc

—

ADTRG0#,

ADTRG1#

PCLKB

tTRGW

R5F5651EDDFM Datasheet(PDF) 132 Page - Renesas Technology Corp

R5F5651EDDFM Datasheet(HTML) 132 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL