R5F5651EDDFM datasheet(135/188 Pages) RENESAS

135 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 135 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

Note:

tPcyc refers to the period of PCLKA in SCI10 and SCI11, and of PCLKB in SCI0 to SCI9, and SCI12.

Note 1. Cb is the total capacitance of the bus lines.

Figure 2.48

Simple IIC Bus Interface Input/Output Timing

Table 2.36

Simple IIC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

Simple IIC

(Standard-mode)

SSCL, SSDA input rise time

tSr

—1000

Figure 2.48

SSCL, SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal

time

tSP

04 × tPcyc

Data input setup time

tSDAS

250

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*1

—

400

Simple IIC

(Fast-mode)

SSCL, SSDA input rise time

tSr

—

300

SSCL, SSDA input fall time

tSf

—

300

SSCL, SSDA input spike pulse removal

time

tSP

04 × tPcyc

Data input setup time

tSDAS

100

—

Data input hold time

tSDAH

0—

SSCL, SSDA capacitive load

Cb*1

—

400

SSDAn

SSCLn

VIH

VIL

tSTAH

tSCLH

tSCLL

P*1

S*1

tSf

tSr

tSCL

tSDAH

tSDAS

tSTAS

tSP

tSTOS

P*1

tBUF

Test conditions

VIH = 0.7 × VCC, VIL = 0.3 × VCC

VOL = 0.6 V, IOL = 6 mA

Sr*1

Note 1. S, P, and Sr indicate the following conditions.

S: Start condition

P: Stop condition

Sr: Restart condition

(n = 0 to 12)

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