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R5F5651EDDFM Datasheet(PDF) 149 Page - Renesas Technology Corp |
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R5F5651EDDFM Datasheet(HTML) 149 Page - Renesas Technology Corp |
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149 / 188 page  R01DS0276EJ0240 Rev.2.40 Page 149 of 188 Oct 31, 2023 RX65N Group, RX651 Group 2. Electrical Characteristics 2.4.7.14 ETHERC Note 1. RMII0_TXD_EN, RMII0_TXD1, RMII0_TXD0 Note 2. RMII0_CRS_DV, RMII0_RXD1, RMII0_RXD0, RMII0_RX_ER Table 2.42 ETHERC Timing Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF, High-drive output is selected by the driving ability control register. Item Symbol Min. Max. Unit Test Conditions ETHERC (RMII) REF50CK cycle time Tck 20 — ns Figure 2.66 to Figure 2.69 REF50CK frequency Typ. 50 MHz — — 50 + 100 ppm MHz REF50CK duty — 35 65 % REF50CK rise/fall time Tckr/ckf 0.5 3.5 ns RMII0_xxxx*1 output delay time Tco 2.5 15.0 ns RMII0_xxxx*2 setup time Tsu 3— ns RMII0_xxxx*2 hold time Thd 1— ns RMII0_xxxx*1, *2 rise/fall time Tr/Tf 0.5 5 ns ET0_WOL output delay time tWOLd 1 23.5 ns Figure 2.70 ETHERC (MII) ET0_TX_CLK cycle time tTcyc 40 — ns — ET0_TX_EN output delay time tTENd 1 20 ns Figure 2.71 ET0_ETXD0 to ET0_ETXD3 output delay time tMTDd 120 ns ET0_CRS setup time tCRSs 10 — ns ET0_CRS hold time tCRSh 10 — ns ET0_COL setup time tCOLs 10 — ns Figure 2.72 ET0_COL hold time tCOLh 10 — ns ET0_RX_CLK cycle time tTRcyc 40 — ns — ET0_RX_DV setup time tRDVs 10 — ns Figure 2.73 ET0_RX_DV hold time tRDVh 10 — ns ET0_ERXD0 to ET0_ERXD3 setup time tMRDs 10 — ns ET0_ERXD0 to ET0_ERXD3 hold time tMRDh 10 — ns ET0_RX_ER setup time tRERs 10 — ns Figure 2.74 ET0_RX_ER hold time tRERh 10 — ns ET0_WOL output delay time tWOLd 1 23.5 ns Figure 2.75 |
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