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R5F5651EDDFM Datasheet(PDF) 147 Page - Renesas Technology Corp |
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R5F5651EDDFM Datasheet(HTML) 147 Page - Renesas Technology Corp |
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147 / 188 page ![]() R01DS0276EJ0240 Rev.2.40 Page 147 of 188 Oct 31, 2023 RX65N Group, RX651 Group 2. Electrical Characteristics Note: tIICcyc: RIIC internal reference clock (IIC) cycle Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by the setting ICFER.NFE = 1. Note 2. Cb is the total capacitance of the bus lines. Figure 2.64 RIIC Bus Interface Input/Output Timing RIIC (Fast-mode+) ICFER.FMPE = 1 SCL input cycle time tSCL 6(12) × tIICcyc + 240 — ns Figure 2.64 SCL input high pulse width tSCLH 3(6) × tIICcyc + 120 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 120 — ns SCL, SDA input rise time tSr —120 ns SCL, SDA input fall time tSf —120 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 120 — ns Start condition input hold time tSTAH tIICcyc + 120 — ns Restart condition input setup time tSTAS 120 — ns Stop condition input setup time tSTOS 120 — ns Data input setup time tSDAS tIICcyc + 20 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb*2 — 550 pF Table 2.40 RIIC Timing (2/2) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, High-drive output is selected by the driving ability control register. Item Symbol Min.*1 Max. Unit Test Conditions SDA0 to SDA2 SCL0 to SCL2 VIH VIL tSTAH tSCLH tSCLL P*1 S*1 tSf tSr tSCL tSDAH tSDAS tSTAS tSP tSTOS P*1 tBUF Test conditions VIH = 0.7 × VCC, VIL = 0.3 × VCC VOL = 0.6 V, IOL = 6 mA (ICFER.FMPE = 0) VOL = 0.4 V, IOL = 15 mA (ICFER.FMPE = 1) Sr*1 Note 1. S, P, and Sr indicate the following conditions. S: Start condition P: Stop condition Sr: Restart condition |
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