R5F5651EDDFM datasheet(154/188 Pages) RENESAS

154 / 188 page

R01DS0276EJ0240 Rev.2.40

Page 154 of 188

Oct 31, 2023

RX65N Group, RX651 Group

2. Electrical Characteristics

2.4.7.15

PDC

Note 1. tPBcyc: PCLKB cycle

Figure 2.76

PDC Input Clock Timing

Figure 2.77

PDC Output Clock Timing

Table 2.43

PDC Timing

Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 V ≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions

PDC

PIXCLK input cycle time

tPIXcyc

—

Figure 2.76

PIXCLK input high pulse width

tPIXH

—

PIXCLK input low pulse width

tPIXL

—

PIXCLK rising time

tPIXr

—5

PIXCLK falling time

tPIXf

—5

PCKO output cycle time

tPCKcyc

2 × tPBcyc

—

Figure 2.77

PCKO output high pulse width

tPCKH

(tPCKcyc – tPCKr – tPCKf)/2 – 3

—

PCKO output low pulse width

tPCKL

(tPCKcyc – tPCKr – tPCKf)/2 – 3

—

PCKO rising time

tPCKr

—5

PCKO falling time

tPCKf

—5

VSYNC/HSYNC input setup time

tSYNCS

—

Figure 2.78

VSYNC/HSYNC input hold time

tSYNCH

5—

PIXD input setup time

tPIXDS

—

PIXD input hold time

tPIXDH

5—

tPIXcyc

tPIXH

tPIXf

tPIXL

tPIXr

PIXCLK input

tPCKcyc

tPCKH

tPCKf

tPCKL

tPCKr

PCKO pin output

R5F5651EDDFM Datasheet(PDF) 154 Page - Renesas Technology Corp

R5F5651EDDFM Datasheet(HTML) 154 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL