S5D3 datasheet(39/89 Pages) RENESAS

39 / 89 page

R01DS0328EU0120 Rev.1.20

Page 39 of 89

Dec 13, 2023

S5D3 Datasheet

2. Electrical Characteristics

2.3.6

Bus Timing

Figure 2.20

Address/data multiplexed bus read access timing

Table 2.18

Bus timing

Conditions:

BCLK = 8 to 120 MHz, EBCLK = 8 to 60 MHz.

VCC = AVCC0 = VCC_USB = VBATT = 2.7 to 3.6 V, VREFH/VREFH0 = 2.7 V to AVCC0.

Output load conditions: VOH = VCC × 0.5, VOL = VCC × 0.5, C = 30 pF.

EBCLK: High drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Others: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

Address delay

tAD

12.5

Figure 2.20 to

Figure 2.25

CS delay

tCSD

12.5

ALE delay time

tALED

12.5

RD delay

tRSD

12.5

Read data setup time

tRDS

12.5

Read data hold time

tRDH

WR0 delay

tWRD

12.5

Write data delay

tWDD

12.5

Write data hold time

tWDH

WAIT setup time

tWTS

12.5

Figure 2.26

WAIT hold time

tWTH

Address bus/

data bus

Data read

(RD)

tAD

EBCLK

Address bus

Address latch

(ALE)

Chip select

(CSn)

tALED

TW1

TW2

Tn1

tAD

tRDS

Tn2

tRSD

TW3

TW4

TW5

Tend

Ta1

Tan

Address cycle

Data cycle

tRDH

tALED

tCSD

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