S5D3 datasheet(2/89 Pages) RENESAS

2 / 89 page

R01DS0328EU0120 Rev.1.20

Page 2 of 89

Dec 13, 2023

S5D3 Datasheet

1. Overview

Overview

The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit cores that share a common set

of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU in this series incorporates a high-performance Arm Cortex®-M4 core running up to 120 MHz with the

following features:

 512-KB code flash memory

 256-KB SRAM

 Capacitive Touch Sensing Unit (CTSU)

 USBFS

 SD/MMC Host Interface

 Quad Serial Peripheral Interface (QSPI)

 Security and safety features

 12-bit A/D Converter (ADC12)

 12-bit D/A Converter (DAC12)

 Analog peripherals.

1.1

Function Outline

Table 1.1

Arm core

Feature

Functional description

Arm Cortex-M4 core

 Maximum operating frequency: up to 120 MHz

 Arm Cortex-M4 core:

- Revision: r0p1-01rel0

- Armv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 Arm Memory Protection Unit (Arm MPU):

- Armv7 Protected Memory System Architecture

- 8 protect regions.

 SysTick timer:

- Driven by SYSTICCLK (LOCO) or ICLK.

Table 1.2

Memory

Feature

Functional description

Code flash memory

512-KB code flash memory. See section 50, Flash Memory in Userʼs Manual.

Data flash memory

8-KB data flash memory. See section 50, Flash Memory in Userʼs Manual.

Memory Mirror Function (MMF)

The Memory Mirror Function (MMF) can be configured to mirror the target application image

load address in code flash memory to the application image link address in the 23-bit unused

memory space (memory mirror space addresses). Your application code is developed and

linked to run from this MMF destination address. Your application code does not need to know

the load location where it is stored in code flash memory. See section 5, Memory Mirror

Function (MMF) in Userʼs Manual.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in Userʼs Manual.

SRAM

On-chip high-speed SRAM with either parity-bit or Error Correction Code (ECC). The first

32 KB of SRAM0 provides error correction capability using ECC. Parity check is performed for

other areas. See section 48, SRAM in Userʼs Manual.

Standby SRAM

On-chip SRAM that can retain data in Deep Software Standby mode. See section 49, Standby

SRAM in Userʼs Manual.

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