S5D3 datasheet(53/89 Pages) RENESAS

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R01DS0328EU0120 Rev.1.20

Page 53 of 89

Dec 13, 2023

S5D3 Datasheet

2. Electrical Characteristics

2.3.11

SPI Timing

Note 1.

tPcyc: PCLKA cycle.

Table 2.25

SPI timing

Conditions:

For RSPCKA and RSPCKB pins, high drive output is selected with the Port Drive Capability bit in the PmnPFS register.

For other pins, middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit*1

Test conditions*2

SPI

RSPCK clock cycle

Master

tSPcyc

2 (PCLKA

 60 MHz)

4 (PCLKA > 60 MHz)

4096

tPcyc

Figure 2.44

C = 30 pF

Slave

4096

RSPCK clock high

pulse width

Master

tSPCKWH (tSPcyc - tSPCKr -

tSPCKf) / 2 - 3

-ns

Slave

2 × tPcyc

RSPCK clock low pulse

width

Master

tSPCKWL (tSPcyc - tSPCKr -

tSPCKf) / 2 - 3

-ns

Slave

2 × tPcyc

RSPCK clock rise and

fall time

Master

tSPCKr,

tSPCKf

-5

Slave

µs

Data input setup time

Master

tSU

Figure 2.45 to

Figure 2.50

C = 30 pF

Slave

Data input hold time

Master

(PCLKA division ratio

set to 1/2)

tHF

Master

(PCLKA division ratio

set to a value other

than 1/2)

tPcyc

Slave

SSL setup time

Master

tLEAD

N × tSPcyc - 10*3

N ×

tSPcyc +

100*3

Slave

6 x tPcyc

-ns

SSL hold time

Master

tLAG

N × tSPcyc - 10 *4

N ×

tSPcyc +

100*4

Slave

6 x tPcyc

-ns

Data output delay

Master

tOD

-6.3

Slave

Data output hold time

Master

tOH

Slave

Successive

transmission delay

Master

tTD

tSPcyc + 2 × tPcyc

8 ×

tSPcyc +

2 × tPcyc

Slave

6 × tPcyc

MOSI and MISO rise

and fall time

Output

tDr, tDf

-5

Input

μs

SSL rise and fall time

Output

tSSLr,

tSSLf

-5

Input

μs

Slave access time

tSA

-2 x tPcyc

+ 28

Figure 2.49 and

Figure 2.50

C = 30PF

Slave output release time

tREL

-2 x tPcyc

+ 28

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