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8SLVP1212 Datasheet(PDF) 14 Page - Renesas Technology Corp

Part # 8SLVP1212
Description  Low Phase Noise, 1-to-12, 3.3V, 2.5V LVPECL Output Fanout Buffer
PDF  24 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

8SLVP1212 Datasheet(HTML) 14 Page - Renesas Technology Corp

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R31DS0036EU0300 MAY 20, 2021
14
©2021 Renesas Electronics Corporation
8SLVP1212 Datasheet
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both differential outputs must meet the VPP and
VCMR input requirements. Figures 3A to 3E show interface examples
for the PCLK/ nPCLK input driven by the most common driver types.
The input interfaces suggested here are examples only. If the driver
is from another vendor, use their termination recommendation.
Please consult with the vendor of the driver component to confirm the
driver termination requirements.
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3E. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
Figure 3D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
PCLK
nPCLK
LVPECL
Input
CML
2.5V
2.5V
2.5V
2.5V
PCLK
nPCLK
2.5V
2.5V
LVPECL
LVPECL
Input
PCLK
nPCLK
PCLK
nPCLK
2.5V
LVPECL
Input
2.5V
CML Built-In Pullup



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