MPC852T datasheet(12/80 Pages) FREESCALE

12 / 80 page

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

Power Supply and Power Sequencing

This section provides design considerations for the MPC852T power supply. The MPC852T has a core

voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH.

The I/O section of the MPC852T is supplied with 3.3 V across VDDH and VSS (GND).

The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI,

TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V

greater than VDDH. In addition, 5-V tolerant pins can not exceed 5.5 V, and the remaining input pins cannot

exceed 3.465 V. This restriction applies to power-on reset or power down and normal operation.

One consequence of multiple power supplies is that when power is initially applied, the voltage rails ramp

up at different rates. The rates depend on the nature of the power supply, the type of load on each power

supply, and the manner in which different voltages are derived. The following restrictions apply:

•VDDL must not exceed VDDH during power-on reset or power down.

•VDDL must not exceed 1.9 V, and VDDH must not exceed 3.465.

These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic

discharge (ESD) protection diodes are forward-biased, and excessive current can flow through these

diodes. If the system power supply design does not control the voltage sequencing, the circuit shown in

Figure 3 can be added to meet these requirements. The MUR420 Schottky diodes control the maximum

potential difference between the external bus and core power supplies on power-on reset, and the 1N5820

diodes regulate the maximum potential difference on power-down.

Figure 3. Example Voltage Sequencing Circuit

10 Mandatory Reset Configurations

The MPC852T requires a mandatory configuration during reset.

If hardware reset configuration word (HRCW) is enabled, by asserting the RSTCONF during HRESET

assertion, the HRCW[DBGC] value that is needed to be set to binary X1 in the hardware reset

configuration word (HRCW) and the SIUMCR[DBGC] should be programmed with the same value in the

boot code after reset.

If hardware reset configuration word (HRCW) is disabled, by negating the RSTCONF during the

HRESET assertion, the SIUMCR[DBGC] should be programmed with binary X1 in the boot code after

reset.

VDDH

VDDL

1N5820

MUR420

MPC852T Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc