PSD813F1V datasheet(79/120 Pages) STMICROELECTRONICS

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Preliminary

PSD813F1-A

9.6.1 Standard JTAG Signals (cont.)

The PSD813F1 supports JTAG In-System-Configuration (ISC) commands, but not

Boundary Scan. A definition of these JTAG-ISC commands and sequences are defined in a

supplemental document available from ST. ST’s PSDsoft software tool and FlashLink JTAG

programming cable implement these JTAG-ISC commands. This document is needed only

as a reference for designers who use a FlashLink to program their PSD813F1.

9.6.2 JTAG Extensions

TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE”

command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are

used to speed programming and erase functions by indicating status on PSD pins instead

of having to scan the status out serially using the standard JTAG channel. See Application

Note 54.

TERR will indicate if an error has occurred when erasing a sector or programming a byte in

Flash memory. This signal will go low (active) when an error condition occurs, and stay

low until an “ISC_CLEAR” command is executed or a chip reset pulse is received after an

“ISC-DISABLE” command. TERR does not apply to EEPROM.

TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be

high when the PSD813F1 device is in read array mode (Flash memory and EEPROM

contents can be read). TSTAT will be low when Flash memory programming or erase cycles

are in progress, and also when data is being written to EEPROM.

TSTAT and TERR can be configured as open-drain type signals during an “ISC_ENABLE”

command. This facilitates a wired-OR connection of TSTAT signals from several PSD813F1

devices and a wired-OR connection of TERR signals from those same devices. This is

useful when several PSD813F1 devices are “chained” together in a JTAG environment.

9.6.3 Security and Flash Memories and EEPROM Protection

When the security bit is set, the device cannot be read on a device programmer or through

the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.

All other program/erase/verify commands are blocked. Full chip erase returns the part to a

non-secured blank state. The Security Bit can be set in PSDsoft Configuration.

All Flash Memory and EEPROM sectors can individually be sector protected against

erasures. The sector protect bits can be set in PSDsoft Configuration.

The

PSD813F1

Functional

Blocks

(cont.)

PSD813F1V Datasheet(PDF) 79 Page - STMicroelectronics