PSD813F1V datasheet(59/120 Pages) STMICROELECTRONICS

59 / 120 page

Preliminary

PSD813F1-A

The

PSD813F1

Functional

Blocks

(cont.)

Control

Direction

Defined In

JTAG

Mode

PSDabel

PSDconfiguration

Setting

Enable

Declare

1 = output,

MCU I/O

pins only

NA*

0 = input

(Note 1)

PLD I/O

Logic

(Note 1)

equations

Data Port

Specify bus type

(Port A)

Address Out

Declare

1 (Note 1)

(Port A,B)

pins only

Address In

Logic equation

(Port A,B,C,D)

for Input

Micro

⇔Cells

Peripheral I/O

Logic equations

PIO bit = 1

(Port A)

(PSEL0 & 1)

JTAG ISP

JTAGSEL

JTAG Configuration

JTAG_

(Note 2)

Enable

Table 21. Port Operating Mode Settings

*NA = Not Applicable

NOTE: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the

individual output enable product term (.oe) from the CPLD AND array.

2. Any of these three methods will enable JTAG pins on Port C.

9.4.2.1 MCU I/O Mode

In the MCU I/O Mode, the microcontroller uses the PSD813F1 ports to expand its own

I/O ports. By setting up the CSIOP space, the ports on the PSD813F1 are mapped into the

microcontroller address space. The addresses of the ports are listed in Table 7.

A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the

Control Register. The MCU I/O direction may be changed by writing to the corresponding

bit in the Direction Register, or by the output enable product term. See the subsection on

the Direction Register in the “Port Registers” section. When the pin is configured as an

output, the content of the Data Out Register drives the pin. When configured as an input,

the microcontroller can read the port input through the Data In buffer. See Figure 25.

Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They

can be used for PLD I/O if equation are written for them in PSDabel.

9.4.2.2 PLD I/O Mode

The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro

⇔Cells, and/or as an

output from the CPLD’s Output Micro

⇔Cells. The output can be tri-stated with a control

signal. This output enable control signal can be defined by a product term from the PLD, or

by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the

Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.

The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an

equation assigning the PLD I/O to a port.

PSD813F1V Datasheet(PDF) 59 Page - STMicroelectronics

PSD813F1V Datasheet(HTML) 59 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL