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NRF52810-QFAA-R Datasheet(PDF) 457 Page - Nordic Semiconductor |
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NRF52810-QFAA-R Datasheet(HTML) 457 Page - Nordic Semiconductor |
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457 / 483 page ![]() Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G F E D C B A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Id RW Field Value Id Value Description DisabledOrRequested 0 RR[4] register is not enabled, or are already requesting reload EnabledAndUnrequested 1 RR[4] register is enabled, and are not yet requesting reload F R RR5 Request status for RR[5] register DisabledOrRequested 0 RR[5] register is not enabled, or are already requesting reload EnabledAndUnrequested 1 RR[5] register is enabled, and are not yet requesting reload G R RR6 Request status for RR[6] register DisabledOrRequested 0 RR[6] register is not enabled, or are already requesting reload EnabledAndUnrequested 1 RR[6] register is enabled, and are not yet requesting reload H R RR7 Request status for RR[7] register DisabledOrRequested 0 RR[7] register is not enabled, or are already requesting reload EnabledAndUnrequested 1 RR[7] register is enabled, and are not yet requesting reload 6.26.4.5 CRV Address offset: 0x504 Counter reload value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Id RW Field Value Id Value Description A RW CRV [0x0000000F..0xFFFFFFFF]Counter reload value in number of cycles of the 32.768 kHz clock 6.26.4.6 RREN Address offset: 0x508 Enable register for reload request registers Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Id H G F E D C B A Reset 0x00000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Id RW Field Value Id Value Description A RW RR0 Enable or disable RR[0] register Disabled 0 Disable RR[0] register Enabled 1 Enable RR[0] register B RW RR1 Enable or disable RR[1] register Disabled 0 Disable RR[1] register Enabled 1 Enable RR[1] register C RW RR2 Enable or disable RR[2] register Disabled 0 Disable RR[2] register Enabled 1 Enable RR[2] register D RW RR3 Enable or disable RR[3] register Disabled 0 Disable RR[3] register Enabled 1 Enable RR[3] register 4430_161 v1.0 457 |
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