NRF52811-QCAA-R7 datasheet(433/444 Pages) NORDIC

433 / 444 page

Hardware and layout

Designator

Value

Description

Footprint

C1, C2

12 pF

Capacitor, NP0, ±2 %

0201

1.2 pF

Capacitor, NP0, ±5 %

0201

C4, C5

100 nF

Capacitor, X5R, ±10 %

0201

100 pF

Capacitor, NP0, ±2 %

0201

4.7 µF

Capacitor, X5R, ±10 %

0603

1.0 µF

Capacitor, X5R, ±5 %

0402

2.2 nH

High frequency chip inductor ±5 %

0201

3.3 nH

High frequency chip inductor ±5 %

0201

10 µH

Chip inductor, IDC,min = 50 mA, ±20 %

0603

15 nH

High frequency chip inductor ±10 %

0402

nRF52811-

CAAA

Multi-protocol Bluetooth® low energy, ANT and 2.4

GHz proprietary system on chip

WLCSP-33

32 MHz

XTAL SMD 2016, 32 MHz, Cl = 8 pF, Total Tol: ±40

ppm

XTAL_2016

Table 133: Bill of material for CAAA WLCSP 2-layer setup

7.3.8 PCB guidelines

A well designed PCB is necessary to achieve good RF performance. Poor layout can lead to loss in

performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks, can be

downloaded from Reference layout nRF52 Series .

To ensure optimal performance it is essential that you follow the schematics and layout references closely.

Especially in the case of the antenna matching circuitry (components between device pin ANT and the

antenna), any changes to the layout can change the behavior, resulting in degradation of RF performance

or a need to change component values. All reference circuits are designed for use with a 50 Ω single-

ended antenna.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal performance.

On PCBs with more than two layers, put a keep-out area on the inner layers directly below the antenna

matching circuitry (components between device pin ANT and the antenna) to reduce the stray

capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna

impedance (normally 50 Ω) to the optimum RF load impedance for the chip. For optimum performance,

the impedance for the matching network should be set as described in the recommended package

reference circuitry in Reference circuitry on page 425 above.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF

capacitors. See the schematics for recommended decoupling capacitor values. The supply voltage for the

chip should be filtered and routed separately from the supply voltages of any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and VDD

bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside RF ground

plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground

plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via

hole should be used for each VSS pin.

4454_140 v1.0

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NRF52811-QCAA-R7 Datasheet(PDF) 433 Page - Nordic Semiconductor

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