NRF52811-QCAA-R7 datasheet(283/444 Pages) NORDIC

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Peripherals

RXD

READY

MISO

MOSI

PSEL.MISO

RXD-1

TXD

TXD+1

PSEL.SCK

PSEL.MOSI

Figure 111: SPI master

RXD-1 and TXD+1 illustrate the double buffered version of RXD and TXD respectively.

6.18.1 Functional description

The TXD and RXD registers are double-buffered to enable some degree of uninterrupted data flow in and

out of the SPI master.

The SPI master does not implement support for chip select directly. Therefore, the CPU must use available

GPIOs to select the correct slave and control this independently of the SPI master. The SPI master supports

SPI modes 0 through 3.

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Leading)

0 (Active high)

SPI_MODE1

0 (Leading)

1 (Active low)

SPI_MODE2

1 (Trailing)

0 (Active high)

SPI_MODE3

1 (Trailing)

1 (Active low)

Table 81: SPI modes

6.18.1.1 SPI master mode pin configuration

The different signals SCK, MOSI, and MISO associated with the SPI master are mapped to physical pins.

This mapping is according to the configuration specified in the PSEL.SCK, PSEL.MOSI, and PSEL.MISO

registers respectively. If the CONNECT field of a PSEL.xxx register is set to Disconnected, the associated SPI

master signal is not connected to any physical pin. The PSEL.SCK, PSEL.MOSI, and PSEL.MISO registers and

their configurations are only used as long as the SPI master is enabled, and retained only as long as the

device is in ON mode. PSEL.SCK, PSEL.MOSI, and PSEL.MISO must only be configured when the SPI master

is disabled.

To secure correct behavior in the SPI, the pins used by the SPI must be configured in the GPIO peripheral

as described in GPIO configuration on page 284 prior to enabling the SPI. The SCK must always be

connected to a pin, and that pin's input buffer must always be connected for the SPI to work. This

configuration must be retained in the GPIO for the selected IOs as long as the SPI is enabled.

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