NRF52811-QCAA-R7 datasheet(284/444 Pages) NORDIC

284 / 444 page

Peripherals

Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in

unpredictable behavior.

SPI master signal

SPI master pin

Direction

Output value

SCK

As specified in PSEL.SCK

Output

Same as CONFIG.CPOL

MOSI

As specified in PSEL.MOSI

Output

MISO

As specified in PSEL.MISO

Input

Not applicable

Table 82: GPIO configuration

6.18.1.2 Shared resources

The SPI shares registers and other resources with other peripherals that have the same ID as the SPI.

Therefore, the user must disable all peripherals that have the same ID as the SPI before the SPI can be

configured and used.

Disabling a peripheral that has the same ID as the SPI will not reset any of the registers that are shared

with the SPI. It is therefore important to configure all relevant SPI registers explicitly to secure that it

operates correctly.

See the Instantiation table in Instantiation on page 18 for details on peripherals and their IDs.

6.18.1.3 SPI master transaction sequence

An SPI master transaction is started by writing the first byte, which is to be transmitted by the SPI master,

to the TXD register.

Since the transmitter is double buffered, the second byte can be written to the TXD register immediately

after the first one. The SPI master will then send these bytes in the order they are written to the TXD

The SPI master is a synchronous interface, and for every byte that is sent, a different byte will be received

at the same time; this is illustrated in SPI master transaction on page 285. Bytes that are received will

be moved to the RXD register where the CPU can extract them by reading the register. The RXD register is

double buffered in the same way as the TXD register, and a second byte can therefore be received at the

same time as the first byte is being extracted from RXD by the CPU. The SPI master will generate a READY

event every time a new byte is moved to the RXD register. The double buffered byte will be moved from

RXD-1 to RXD as soon as the first byte is extracted from RXD. The SPI master will stop when there are no

more bytes to send in TXD and TXD+1.

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