NRF52811-QCAA-R datasheet(366/444 Pages) NORDIC

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Peripherals

To secure correct behaviour of the TWI slave, PSEL.SCL, PSEL.SDA, CONFIG and the ADDRESS[n] registers,

must be configured prior to enabling the TWI slave through the ENABLE register. Similarly, changing these

settings must be performed while the TWI slave is disabled. Failing to do so may result in unpredictable

behaviour.

6.26.1 EasyDMA

The TWIS implements EasyDMA for accessing RAM without CPU involvement.

The TWIS peripheral implements the following EasyDMA channels:

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 108: TWIS EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 35.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

6.26.2 TWI slave responding to a read command

Before the TWI slave can respond to a read command the TWI slave must be configured correctly and

enabled via the ENABLE register. When enabled the TWI slave will be in its IDLE state where it will

consume IIDLE .

A read command is started when the TWI master generates a start condition on the TWI bus, followed

by clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is

followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.

The TWI slave is able to listen for up to two addresses at the same time. Which addresses to listen for is

configured in the ADDRESS registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the read command if the address presented by the master

matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ

event when it acknowledges the read command.

The TWI slave is only able to detect a read command from the IDLE state.

The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.

When the read command is received the TWI slave will enter the TX state if the internal 'TX prepared' flag

is set.

If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch

the master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.

The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when it

enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the

master using the master's clock. The TWI slave will consume ITX in this mode.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the

TX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event

will be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag

('unprepare TX') and go back to the IDLE state when it has stopped.

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