NRF52811-QCAA-R datasheet(369/444 Pages) NORDIC

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Peripherals

It is here assumed that the receiver does not know in advance what the master wants to read, and

that this information is provided in the first two bytes received in the write part of the repeated start

sequence. To guarantee that the CPU is able to process the received data before the TWI slave starts to

reply to the read command, the SUSPEND task is triggered via a shortcut from the READ event generated

when the read command is received. When the CPU has processed the incoming data and prepared the

correct data response, the CPU will resume the transaction by triggering the RESUME task.

ADDR

Figure 142: A repeated start sequence, where the TWI master

writes two bytes followed by reading four bytes from the slave

6.26.5 Terminating an ongoing TWI transaction

In some situations, e.g. if the external TWI master is not responding correctly, it may be required to

terminate an ongoing transaction.

This can be achieved by triggering the STOP task. In this situation a STOPPED event will be generated when

the TWI has stopped independent of whether or not a STOP condition has been generated on the TWI bus.

The TWI slave will release the bus when it has stopped and go back to its IDLE state.

6.26.6 Low power

When putting the system in low power and the peripheral is not needed, lowest possible power

consumption is achieved by stopping, and then disabling the peripheral.

The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,

software shall wait until the STOPPED event was received as a response before disabling the peripheral

through the ENABLE register.

6.26.7 Slave mode pin configuration

The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the

configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is

enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins

will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and

when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in GPIO

configuration before enabling peripheral on page 370.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

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NRF52811-QCAA-R Datasheet(PDF) 369 Page - Nordic Semiconductor