ST7FLITE25F2M6 datasheet(70/131 Pages) STMICROELECTRONICS

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11.4 SERIAL PERIPHERAL INTERFACE (SPI)

11.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full-

duplex, synchronous, serial communication with

external devices. An SPI system may consist of a

master and one or more slaves or a system in

which devices may be either masters or slaves.

11.4.2 Main Features

Full duplex synchronous transfers (on 3 lines)

Simplex synchronous transfers (on 2 lines)

Master or slave operation

Six master mode frequencies (fCPU/4 max.)

fCPU/2 max. slave mode frequency

SS Management by software or hardware

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision, Master Mode Fault and Overrun

flags

11.4.3 General Description

Figure 42 shows the serial peripheral interface

(SPI) block diagram. There are 3 registers:

– SPI Control Register (SPICR)

– SPI Control/Status Register (SPICSR)

– SPI Data Register (SPIDR)

The SPI is connected to external devices through

3 pins:

– MISO: Master In / Slave Out data

– MOSI: Master Out / Slave In data

– SCK: Serial Clock out by SPI masters and in-

put by SPI slaves

–SS: Slave select:

This input signal acts as a ‘chip select’ to let

the SPI master communicate with slaves indi-

vidually and to avoid contention on the data

lines. Slave SS inputs can be driven by stand-

ard I/O ports on the master Device.

Figure 42. Serial Peripheral Interface Block Diagram

SPIDR

Read Buffer

8-Bit Shift Register

Write

Read

Data/Address Bus

SPI

SPIE

SPE

MSTR

CPHA

SPR0

SPR1

CPOL

SERIAL CLOCK

GENERATOR

MOSI

MISO

SCK

CONTROL

STATE

SPICR

SPICSR

Interrupt

request

MASTER

CONTROL

SPR2

SPIF WCOL

MODF

OVR

SSI

SSM

SOD

bit

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