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ST7FLITE25F2M6 Datasheet(PDF) 98 Page - STMicroelectronics |
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ST7FLITE25F2M6 Datasheet(HTML) 98 Page - STMicroelectronics |
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98 / 131 page ![]() ST7LITE2 98/131 OPERATING CONDITIONS (Cont’d) Figure 57. PLL ∆f CPU/fCPU versus time Figure 58. PLLx4 Output vs CLKIN frequency Note: fOSC = fCLKIN/2*PLL4 Figure 59. PLLx8 Output vs CLKIN frequency Note: fOSC = fCLKIN/2*PLL8 13.3.4.3 32MHz PLL TA = -40 to 125°C, unless otherwise specified Note 1: 32 MHz is guaranteed within this voltage range. tw(JIT) ∆f CPU/fCPU t Min Max 0 tw(JIT) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 1 1.5 2 2.5 3 External Input Clock Frequency (MHz) 3.3 3 2.7 1.00 3.00 5.00 7.00 9.00 11.00 0.85 0.9 1 1.5 2 2.5 External Input Clock Frequency (MHz) 5.5 5 4.5 4 Symbol Parameter Min Typ Max Unit VDD Voltage 1) 4.5 5 5.5 V fPLL32 Frequency 1) 32 MHz fINPUT Input Frequency 7 89 MHz 1 |
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