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ST7FLITE25F2M6 Datasheet(PDF) 29 Page - STMicroelectronics |
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ST7FLITE25F2M6 Datasheet(HTML) 29 Page - STMicroelectronics |
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29 / 131 page  ST7LITE2 29/131 7.6 SYSTEM INTEGRITY MANAGEMENT (SI) The System Integrity Management block contains the Low voltage Detector (LVD) and Auxiliary Volt- age Detector (AVD) functions. It is managed by the SICSR register. 7.6.1 Low Voltage Detector (LVD) The Low Voltage Detector function (LVD) gener- ates a static reset when the VDD supply voltage is below a VIT-(LVD) reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset. The VIT-(LVD) reference value for a voltage drop is lower than the VIT+(LVD) reference value for power- on in order to avoid a parasitic reset when the MCU starts running and sinks current on the sup- ply (hysteresis). The LVD Reset circuitry generates a reset when VDD is below: –VIT+(LVD)when VDD is rising –VIT-(LVD) when VDD is falling The LVD function is illustrated in Figure 17. The voltage threshold can be configured by option byte to be low, medium or high. Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD), the MCU can only be in two modes: – under full software control – in static safe reset In these conditions, secure operation is always en- sured for the application without the need for ex- ternal reset hardware. During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices. Notes: The LVD allows the device to be used without any external RESET circuitry. The LVD is an optional function which can be se- lected by option byte. Figure 17. Low Voltage Detector vs Reset VDD VIT+(LVD) RESET VIT-(LVD) Vhys 1 |
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