EMC646SP16JS-10LL datasheet(16/65 Pages) EMLSI

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EMC646SP16J

4Mx16 CellularRAM

Preliminary

Low-Power Operation

Standby Mode Operation

During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby

operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or

when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the

address or control inputs.

Temperature Compensated Refresh

Temperature compensated refresh (TCR) allows for adequate refresh at different temperatures. This CellularRAM device includes an

on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually

adjusts the refresh rate to match that temperature.

Partial Array Refresh

Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce

standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half

array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the

end of the address map. (See Table 11) READ and WRITE operations to address ranges receiving refresh will not be affected. Data

stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new portions are

available immediately upon writing to the RCR.

Deep Power-Down Operation

Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not require the storage

provided by the CellularRAM device. Any stored data will become corrupted when DPD is enabled. When refresh activity has been re-

enabled, the CellularRAM device will require 150

µs to perform an initialization procedure before normal operations can resume. During

this 150

µs period, the current consumption will be higher than the specified standby levels, but considerably lower than the active

current specification. DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE#

goes HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10

µs.

Registers

Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the Cellular-

RAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh

configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded

with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides

information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.

Access Using CRE

The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input

is HIGH. (See Figure 10 through 13) When CRE is LOW, a READ or WRITE operation will access the memory array. The configuration

register values are written via addresses A[21:0]. In an asynchronous WRITE, the values are latched into the configuration register on

the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”. The BCR is accessed when A[19:18] are

10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b. For reads, address inputs other than

A[19:18] are “Don’t Care”, and register bits 15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or

WRITE operation, reading the memory array is highly recommended.

EMC646SP16JS-10LL Datasheet(PDF) 16 Page - Emerging Memory & Logic Solutions Inc

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