EMC646SP16JS-10LL datasheet(25/65 Pages) EMLSI

25 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Latency Counter (BCR[13:11]) Default = Three Clock Latency

The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data

value transferred. For allowable latency codes, see Tables 5 and 6, respectively, and Figures 18 and 19, respectively.

Initial Access Latency (BCR[14]) Default = Variable

Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to

detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that

allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is

not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency

counter. (See Table 6 and Figure 19)

Table 5: Variable Latency Configuration Codes

Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.

Figure18: Latency Counter (Variable Initial Latency, No Refresh Collision)

BCR[13:11]

Latency

Configuration

Code

Latency 1

Max Input CLK Frequency (MHz)

Normal

Refresh Collision

104

010

2 (3 clocks)

66(15ns)

52(19.2ns)

40(25ns)

011

3 (4 clocks)-default

104(9.62ns)

83(12ns)

66(15ns)

Others

Reserved

VIH

VIL

VIH

VIL

VOH

VOL

CLK

A[21:0]

ADV#

Code 2

Code 3

(default)

VOH

VOL

DQ[15:0]

Don’t Care

Undefined

Valid

Address

VIH

VIL

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

Valid

Output

EMC646SP16JS-10LL Datasheet(PDF) 25 Page - Emerging Memory & Logic Solutions Inc

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