EMC646SP16JS-10LL datasheet(32/65 Pages) EMLSI

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EMC646SP16J

4Mx16 CellularRAM

Preliminary

Table 14: Burst READ Cycle Timing Requirements

All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).

Note:

1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#

HIGH, or b) CE# HIGH for longer than 15ns.

2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.

3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.

Parameter

Symbol

104MHz

83MHz

66MHZ

Unit

Note

Min

Max

Min

Max

Min

Max

Address access time (fixed latency)

tAA

ADV# access time (fixed latency)

tAADV

Burst to READ access time (variable latency)

tABA

35.9

CLK to output delay

tACLK

Address hold from ADV# HIGH(fixed latency)

tAVH

222

Burst OE# LOW to output delay

tBOE

CE# HIGH between subsequent burst or mixed mode

operations

tCBPH

568

Maximum CE# pulse width

tCEM

444

µs

CE# or ADV# LOW to WAIT valid

tCEW

17.5

7.5

CLK period

tCLK

9.62

12.5

Chip select access time (fixed latency)

tCO

CE# setup time to active CLK edge

tCSP

345

Hold time from active CLK edge

tHD

222

Chip disable to DQ and WAIT High-Z output

tHZ

888

CLK rise or fall time

tKHKL

1.6

1.8

2.0

CLK to WAIT valid

tKHTL

Output HOLD from CLK

tKOH

222

CLK HIGH or LOW time

tKP

345

Output disable to DQ High-Z output

tOHZ

888

Output enable to Low-Z output

tOLZ

333

Setup time to active CLK edge

tSP

333

EMC646SP16JS-10LL Datasheet(PDF) 32 Page - Emerging Memory & Logic Solutions Inc

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