EMC646SP16J

4Mx16 CellularRAM

13

Preliminary

Figure 7: Burst Mode WRITE (4-word burst)

Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency; latency code 2 (3 clocks); WAIT active LOW; WAIT asserted during delay.

The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen,

or thirty-two words. Continuous bursts have the ability to start at a specified address and burst to the end of the row ( 128 or 256 words,

determined by the manufacturer).

The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between

the processor and CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE

operations always use fixed latency). Variable latency allows the CellarRAM to be configured for minimum latency at high clock

frequencies, but the controller must monitor WAIT to detect any conflict with refresh cycles.

Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency

time and clock speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency

also provides improved performance at lower clock frequencies.

The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory.

WAIT will again be asserted at the boundary of the row, unless wrapping within the burst length.

To access other devices on the same bus without the timing penalty of the initial latency for a new burst, burst mode can be suspended.

Bursts are suspended by stopping CLK. CLK can be stopped HIGH or LOW. If another device will use the data bus while the burst is

suspended, OE# should be taken HIGH to disable the CellularRAM outputs; otherwise, OE# can remain LOW. Note that the WAIT

output will continue to be active, and as a result no other devices should directly share the WAIT connection to the controller. To

continue the burst sequence, OE# is taken LOW, then CLK is restarted after valid data is available on the bus. The CE# LOW time is

CLK

Latency Code 2(3 clocks)

Don’t Care

WRITE Burst Identified

(WE# = LOW)

A[21:0]

ADV#

WE#

LB#/UB#

WAIT

DQ[15:0]

Address

Valid

D0

D1

D2

D3

CE#

OE#