EMC646SP16JS-90L datasheet(22/65 Pages) EMLSI

22 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Bus Configuration Register

The BCR defines how the CellularRAM device interacts with the system memory bus. Page mode operation is enabled by a bit contained in the RCR. Fig-

ure 16 describes the control bit BCR. At power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the

Figure 16: Bus Configuration Register Definition

Note: 1. Burst wrap and length apply to both READ and WRITE operations.

A[21:20]

A[19:18]

A[17:16]

A15

A14

A13 A12 A11

A10

A2 A1 A0

21-20

19-18

17-16

Reserved

Select

Reserved

Operating

Mode

Initial

Latency

Counter

WAIT

Polarity

Reserved

WAIT

Configuration(WC)

Reserved

Drive

Strength

Burst

Wrap(BW)*

Burst

Length(BL)*

BCR[14]

Initial Access Latency

BCR[3]

Burst Wrap (Note 1)

Variable (default)

Burst wraps within the burst length

Fixed

Burst no wrap (default)

BCR[5]

BCR[4]

Drive Strength

BCR[13]

BCR[12]

BCR[11]

Latency Counter

Full

Code 0 - Reserved

1/2 (default)

Code 1 - Reserved

1/4

Code 2

Reserved

Code 3 (default)

100

Code 4

101

Code 5

BCR[8]

WAIT Configuration

110

Code 6

Asserted during delay

Code 7 - Reserved

Asserted one data before delay(default)

BCR[10]

WAIT Polarity

Active LOW

Active HIGH (default)

BCR[15]

Operating Mode

Synchronous burst access mode

BCR[2]

BCR[1]

BCR[0]

Burst Length (Note 1)

Asynchronous access mode (default)

4 words

8 words

BCR[19]

BCR[18]

16 words

Select RCR

32 words

Select BCR

Continuous burst (default)

Select DIDR

Others

Reserved

Must be set to “0”

All must be set to “0”

EMC646SP16JS-90L Datasheet(PDF) 22 Page - Emerging Memory & Logic Solutions Inc

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