EMC646SP16JS-90L datasheet(20/65 Pages) EMLSI

Part #	EMC646SP16JS-90L

Description	4Mx16 bit CellularRAM

PDF	65 Pages

Scroll/Zoom	100%

Manufacturer	EMLSI [Emerging Memory & Logic Solutions Inc]

Direct Link	http://www.emlsi.com

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20 / 65 page

EMC646SP16J

4Mx16 CellularRAM

Preliminary

Figure 13: Register READ, Synchronous Mode, Followed by READ ARRAY Operation (WE# HIGH)

Note:

1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks);

WAIT active LOW; WAIT asserted during delay.

2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.

3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require

a corresponding number of additional CE# LOW cycles.

CE#

A[21:0]

ADV#

OE#

DQ[15:0]

A[19:18]2

CRE

CLK

WAIT

tCBPH

Latch control register value

Latch control register address

tSP

(except A[19:18])

tHZ

tOHZ

LB#/UB#

tHD

Data

Valid

tBOE

tACLK

tOLZ

tSP

tHD

tSP

tHD

tCSP

tABA

WE#

tSP

High-Z

tCW

tKOH

Don’t Care

Undefined

CR Valid

Address

EMC646SP16JS-90L Datasheet(PDF) 20 Page - Emerging Memory & Logic Solutions Inc

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