7547 datasheet(45/91 Pages) RENESAS

45 / 91 page

Rev.1.21

Nov 15, 2006

page 45 of 89

REJ03B0156-0121

7547 Group

Fig. 53 Block diagram of clock synchronous serial I/O2

Fig. 54 Operation of clock synchronous serial I/O2 function

qSerial I/O2

Serial I/O2 can be used as either clock synchronous or asynchro-

nous (UART) serial I/O. A dedicated timer is also provided for

baud rate generation.

(1) Clock Synchronous Serial I/O2 Mode

Clock synchronous serial I/O2 mode can be selected by setting

the serial I/O2 mode selection bit of the serial I/O2 control register

(bit 6) to “1”.

For clock synchronous serial I/O2, the transmitter and the receiver

must use the same clock. If an internal clock is used, transfer is

started by a write signal to the TB/RB.

RBF = 1

TSC = 1

TBE = 0

TBE = 1

TSC = 0

Transfer shift clock

(1/2 to 1/2048 of the internal

clock, or an external clock)

Serial output TxD2

Serial input RxD2

Write pulse to receive/transmit

buffer register 2 (address 002E16)

Overrun error (OE)

detection

Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after

the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the

serial I/O2 control register.

2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial

data is output continuously from the TxD2 pin.

3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .

Receive enable signal SRDY2

1/4

F/F

P06/SCLK2

Serial I/O2 status register

Serial I/O2 control register

P07/SRDY2

P04/RXD2

P05/TXD2

XIN

Receive buffer register 2

Address 002E16

Receive shift register 2

Receive buffer full flag (RBF)

Receive interrupt request (RI)

Clock control circuit

Shift clock

Serial I/O2 synchronous

clock selection bit

Frequency division ratio 1/(n+1)

Baud rate generator 2

Address 003216

BRG count source selection bit

Clock control circuit

Falling-edge detector

Transmit buffer register 2

Data bus

Address 002E16

Shift clock

Transmit shift completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Transmit interrupt source selection bit

Address 002F16

Data bus

Address 003016

Transmit shift register 2

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