7547 datasheet(16/91 Pages) RENESAS

16 / 91 page

7547 Group

Rev.1.21

Nov 15, 2006

page 16 of 89

REJ03B0156-0121

Fig. 14 Block diagram of ports (2)

(8) Port P10

Direction

Data bus

Port latch

Serial I/O1 enable bit

Receive enable bit

Serial I/O1 input

Capture 0 input control

P10, P12, P13

input level

selection bit

Capture 0 input

P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.

When the TTL level is selected, there is no hysteresis characteristics.

(9) Port P11

Data bus

Port latch

Serial I/O1 output

P11/TxD1 P-channel output disable bit

Direction

Serial I/O1 enable bit

Transmit enable bit

(10) Port P12

Serial I/O1 clock output

Serial I/O1 mode selection bit

Serial I/O1 enable bit

Serial I/O1 synchronous

clock selection bit

Direction

Data bus

Port latch

Serial I/O1 clock input

P10, P12, P13

input level

selection bit

(12) Port P14

Data bus

Serial I/O1 ready output

Port latch

Direction

CNTR0 interrupt input

Timer output

P10, P12, P13

input level

selection bit

Serial I/O1 mode selection bit

Serial I/O1 enable bit

SRDY1 output enable bit

Data bus

Port latch

Direction

(11) Port P13

Data bus

Port latch

Direction

A/D converter input

Analog input pin

selection bit

(13) Ports P20–P27

Pulse output mode

7547 Datasheet(PDF) 16 Page - Renesas Technology Corp

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