 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS72011RB120FPV Datasheet(PDF) 177 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
DS72011RB120FPV Datasheet(HTML) 177 Page - Renesas Technology Corp |
|
|
177 / 1196 page  Section 6 Interrupt Controller (INTC) Rev. 2.00 Sep. 07, 2007 Page 149 of 1164 REJ09B0321-0200 6.7 Interrupt Response Time Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the interrupt exception service routine begins. The interrupt processing operations differ in the cases when banking is disabled, when banking is enabled without register bank overflow, and when banking is enabled with register bank overflow. Figures 6.4 and 6.5 show examples of pipeline operation when banking is disabled. Figures 6.6 and 6.7 show examples of pipeline operation when banking is enabled without register bank overflow. Figures 6.8 and 6.9 show examples of pipeline operation when banking is enabled with register bank overflow. Table 6.5 Interrupt Response Time Number of States Item NMI User Break H-UDI IRQ, PINT Peripheral Module Remarks Time from occurrence of interrupt request until interrupt controller identifies priority, compares it with mask bits in SR, and sends interrupt request signal to CPU 2 Icyc + 2 Bcyc + 1 Pcyc 3 Icyc 2 Icyc + 1 Pcyc 2 Icyc + 3 Bcyc + 1 Pcyc 2 Icyc + 1 Bcyc + 1 Pcyc Min. 3 Icyc + m1 + m2 No register banking Max. 4 Icyc + 2 (m1 + m2) + m3 Min. is when the interrupt wait time is zero. Max. is when a higher- priority interrupt request has occurred during interrupt exception handling. Min. 3 Icyc + m1 + m2 Register banking without register bank overflow Max. 12 Icyc + m1 + m2 Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. Min. 3 Icyc + m1 + m2 Time from input of interrupt request signal to CPU until sequence currently being executed is completed, interrupt exception handling starts, and first instruction in interrupt exception service routine is fetched Register banking with register bank overflow Max. 3 Icyc + m1 + m2 + 19 (m4) Min. is when the interrupt wait time is zero. Max. is when an interrupt request has occurred during execution of the RESBANK instruction. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
