R5F72115D160FPV datasheet(541/1228 Pages) RENESAS

541 / 1228 page

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 517 of 1200

REJ09B0344-0200

(4)

Complementary PWM Mode Output Protection Function

Complementary PWM mode output has the following protection functions.

(a)

With the exception of the buffer registers, which can be rewritten at any time, access by the CPU

can be enabled or disabled for the mode registers, control registers, compare registers, and

counters used in complementary PWM mode by means of the RWE bit in the timer read/write

enable register (TRWER). The applicable registers are some (21 in total) of the registers in

channels 3 and 4 shown in the following:

• TCR_3 and TCR_4, TMDR_3 and TMDR_4, TIORH_3 and TIORH_4, TIORL_3 and

TIORL_4, TIER_3 and TIER_4, TCNT_3 and TCNT_4, TGRA_3 and TGRA_4, TGRB_3

and TGRB_4, TOER, TOCR, TGCR, TCDR, and TDDR.

This function enables miswriting due to CPU runaway to be prevented by disabling CPU access to

the mode registers, control registers, and counters. When the applicable registers are read in the

access-disabled state, undefined values are returned. Writing to these registers is ignored.

(b)

Halting of PWM output by external signal

The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting

specified external signals. There are four external signal input pins.

See section 12, Port Output Enable 2 (POE2), for details.

R5F72115D160FPV Datasheet(PDF) 541 Page - Renesas Technology Corp