R5F72115D160FPV datasheet(543/1228 Pages) RENESAS

543 / 1228 page

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)

Rev. 2.00 May. 08, 2008 Page 519 of 1200

REJ09B0344-0200

• Basic Operation Example of A/D Converter Start Request Delaying Function

Figure 10.80 shows a basic example of A/D converter request signal (TRG4AN) operation

when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter

start request signal is output during TCNT_4 down-counting.

TADCORA_4

TADCOBRA_4

TCNT_4

Transfer from cycle buffer

A/D converter start request

(TRG4AN)

(Complementary PWM mode)

Figure 10.80 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation

• Buffer Transfer

The data in the timer A/D converter start request cycle set registers (TADCORA_4 and

TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set

buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer

registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits

in the timer A/D converter start request control register (TADCR_4).

• A/D Converter Start Request Delaying Function Linked with Interrupt Skipping

A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with

interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in

the timer A/D converter start request control register (TADCR).

Figure 10.81 shows an example of A/D converter start request signal (TRG4AN) operation

when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D

converter start requests are linked with interrupt skipping.

Figure 10.82 shows another example of A/D converter start request signal (TRG4AN)

operation when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter

start requests are linked with interrupt skipping.

R5F72115D160FPV Datasheet(PDF) 543 Page - Renesas Technology Corp