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R5F72115D160FPV Datasheet(PDF) 587 Page - Renesas Technology Corp |
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R5F72115D160FPV Datasheet(HTML) 587 Page - Renesas Technology Corp |
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587 / 1228 page ![]() Section 10 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 2.00 May. 08, 2008 Page 563 of 1200 REJ09B0344-0200 10.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.133 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. Counter clear signal TCNT TCNT input clock H'FFFF H'0000 TGF TCFV Disabled MP φ Figure 10.133 Contention between Overflow and Counter Clearing |
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