R5F72115D160FPV datasheet(709/1228 Pages) RENESAS

709 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 685 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

RDF

R/(W)* Receive FIFO Data Full

Indicates that receive data has been transferred to the

receive FIFO data register (SCFRDR), and the

quantity of data in SCFRDR has become more than

the receive trigger number specified by the RTRG[1:0]

bits in the FIFO control register (SCFCR).

0: The quantity of transmit data written to SCFRDR is

less than the specified receive trigger number

[Clearing conditions]

• RDF is cleared to 0 by a power-on reset, standby

mode

• RDF is cleared to 0 when the SCFRDR is read

until the quantity of receive data in SCFRDR

becomes less than the specified receive trigger

number after 1 is read from RDF and then 0 is

written

• RDF is cleared to 0 when SCFRDR is read by the

DMAC until the quantity of receive data in

SCFRDR becomes less than the specified receive

trigger number.

1: The quantity of receive data in SCFRDR is more

than the specified receive trigger number

[Setting condition]

• RDF is set to 1 when a quantity of receive data

more than the specified receive trigger number is

stored in SCFRDR*

Note: * As SCFTDR is a 16-byte FIFO register, the

maximum quantity of data that can be read

when RDF is 1 becomes the specified

receive trigger number. If an attempt is made

to read after all the data in SCFRDR has

been read, the data is undefined. The

quantity of receive data in SCFRDR is

indicated by the lower 8 bits of SCFDR.

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