R5F72115D160FPV datasheet(710/1228 Pages) RENESAS

710 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 686 of 1200

REJ09B0344-0200

Bit

Bit Name

Initial

Value

R/W

Description

R/(W)* Receive Data Ready

Indicates that the quantity of data in the receive FIFO

data register (SCFRDR) is less than the specified

receive trigger number, and that the next data has not

yet been received after the elapse of 15 ETU from the

last stop bit in asynchronous mode. In clocked

synchronous mode, this bit is not set to 1.

0: Receiving is in progress, or no receive data

remains in SCFRDR after receiving ended normally

[Clearing conditions]

• DR is cleared to 0 when the chip undergoes a

power-on reset

• DR is cleared to 0 when all receive data are read

after 1 is read from DR and then 0 is written.

• DR is cleared to 0 when all receive data in

SCFRDR are read by the DMAC.

1: Next receive data has not been received

[Setting condition]

• DR is set to 1 when SCFRDR contains less data

than the specified receive trigger number, and the

next data has not yet been received after the

elapse of 15 ETU from the last stop bit.*

Note: * This is equivalent to 1.5 frames with the 8-bit,

1-stop-bit format. (ETU: elementary time unit)

Note:

Only 0 can be written to clear the flag after 1 is read.

R5F72115D160FPV Datasheet(PDF) 710 Page - Renesas Technology Corp