R5F72115D160FPV datasheet(711/1228 Pages) RENESAS

711 / 1228 page

Section 15 Serial Communication Interface with FIFO (SCIF)

Rev. 2.00 May. 08, 2008 Page 687 of 1200

REJ09B0344-0200

15.3.8

Bit Rate Register (SCBRR)

SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the

CKS[1:0] bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate.

The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.

Each channel has independent baud rate generator control, so different values can be set in four

channels.

7654321

11111111

R/W

Bit:

Initial value:

R/W:

The SCBRR setting is calculated as follows:

• Asynchronous mode:

(1) In normal mode (when the ABCS bit in SCSEMR is 0)

N =

× 106 − 1

× 22n-1 × B

(2) In serial extended mode (when the ABCS bit in SCSEMR is 1)

N =

× 106 − 1

× 22n-1 × B

• Clocked synchronous mode:

N =

× 106 − 1

× 22n-1 × B

B: Bit rate (bits/s)

N: SCBRR setting for baud rate generator (0

≤ N ≤ 255)

(The setting must satisfy the electrical characteristics.)

φ: Operating frequency for peripheral modules (MHz)

n: Baud rate generator clock source (n

= 0, 1, 2, 3) (for the clock sources and values of n,

see table 15.3.)

R5F72115D160FPV Datasheet(PDF) 711 Page - Renesas Technology Corp