R5F72115D160FPV datasheet(818/1228 Pages) RENESAS

818 / 1228 page

Section 17 A/D Converter (ADC)

Rev. 2.00 May. 08, 2008 Page 794 of 1200

REJ09B0344-0200

17.7.5

Notes on Noise Countermeasures

To prevent damage due to an abnormal voltage, such as an excessive surge at the analog input pins

(AN0 to AN7) and analog reference power supply (AVREF), a protection circuit should be

connected between the AVcc and AVss, as shown in figure 17.8. The AVREFVss and AVss

should be the same voltage. Also, the bypass capacitors connected to AVREF and the filter

capacitor connected to ANn should be connected to the AVss. If a filter capacitor is connected as

shown in figure 17.8, the input currents at the analog input pin (ANn) are averaged, and an error

may occur. Careful consideration is therefore required when deciding the circuit constants.

4.5 V to 5.5 V

GND

μF

0.1

μF

0.1

μF

Analog input pin

(channel 0 to 7)

100

0.1

μF

AVCC

AVSS

AVREFH

AVREFVSS

AN0 to AN7

SH7211F

Figure 17.8 Example of Analog Input Pin Protection Circuit

17.7.6

Notes on Register Setting

• Set the ADST bit in the A/D control register (ADCR) after the A/D start trigger select register

(ADSTRGR) and the A/D analog input channel select register (ADANSR) have been set. Do

not modify the settings of the ADCS, ACE, ADIE, TRGE, and EXTRG bits while the ADST

bit in the ADCR register is set to 1.

• Do not start the A/D conversion when the ANS bits (ANS[7:0]) in the A/D analog input

channel select register (ADANSR) are all 0.

17.7.7

Treatment of AVcc and AVss When the A/D Converter is Not Used

When the A/D converter is not used, it is recommended that AVcc be connected to VccQ and

AVss be connected to VssQ.

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