R5F72115D160FPV datasheet(956/1228 Pages) RENESAS

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Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 932 of 1200

REJ09B0344-0200

(3)

Erasing Procedure in User Program Mode

The procedures for download, initialization, and erasing are shown in figure 21.12.

Start erasing procedure

program

Select on-chip program

to be downloaded and

set download destination

by FTDAR

Set FKEY to H'A5

After clearing VBR,

set SCO to 1 and

execute download

DPFR = 0?

Yes

Download error processing

Set the FPEFEQ and

FUBRA parameters

Initialization

JSR FTDAR setting+32

Yes

End erasing

procedure program

FPFR=0 ?

Initialization error processing

Clear FKEY to 0

Set FEBS parameter

Erasing

JSR FTDAR setting+16

Yes

FPFR=0 ?

Clear FKEY and erasing

error processing

Yes

Required block

erasing is

completed?

Set FKEY to H'5A

Clear FKEY to 0

(3.1)

(3.2)

(3.3)

(3.4)

(3.5)

(3.6)

Set internal clock ratio by

frequency control register

(FRQCR) to 4:4:4

Figure 21.12 Erasing Procedure

The details of the erasing procedure are described below. The procedure program must be

executed in an area other than the user MAT to be erased.

Especially the part where the SCO bit in FCCS is set to 1 for downloading must be executed in on-

chip RAM.

The area that can be executed in the steps of the user procedure program (on-chip RAM, user

MAT, and external space) is shown in section 21.8.2, Areas for Storage of the Procedural Program

and Data for Programming.

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