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R5F72115D160FPV Datasheet(PDF) 959 Page - Renesas Technology Corp

Part # R5F72115D160FPV
Description  32-Bit RISC Microcomputer SuperHTM RISC engine Family
PDF  1228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F72115D160FPV Datasheet(HTML) 959 Page - Renesas Technology Corp

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Section 21 Flash Memory
Rev. 2.00 May. 08, 2008 Page 935 of 1200
REJ09B0344-0200
Download and initialization are performed only once at the beginning.
In this kind of operation, note the following:
1. Be careful not to destroy on-chip RAM with overlapped settings.
In addition to the erasing program area and programming program area, areas for the user
procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make
settings that will overwrite data in these areas.
2. Be sure to initialize both the erasing program and programming program.
Initialization by setting the FPEFEQ and FUBRA parameters must be performed for both
the erasing program and the programming program. Initialization must be executed for
both entry addresses: (download start address for erasing program) + 32 bytes
(H'FFF81020 in this example) and (download start address for programming program) + 32
bytes (H'FFF82020 in this example).
21.5.3
User Boot Mode
This LSI has user boot mode which is initiated with different mode pin settings than those in user
program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that
uses the on-chip SCIF.
Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the
user boot MAT is only enabled in boot mode or programmer mode.
(1)
User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 21.1.
When the reset start is executed in user boot mode, the check routine for flash-memory related
registers runs on the on-chip RAM. NMI and all other interrupts cannot be accepted. Neither can
the AUD be used in this period. This period is 100
μs while operating at an internal frequency of
40 MHz.
Next, processing starts from the execution start address of the reset vector in the user boot MAT.
At this point, H'AA is set to the flash MAT select register (FMATS) because the execution MAT
is the user boot MAT.



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