R5F72115D160FPV datasheet(953/1228 Pages) RENESAS

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Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 929 of 1200

REJ09B0344-0200

(2.6) The operating frequency is set to the FPEFEQ parameter and the user branch destination is

set to the FUBRA parameter for initialization.

1. The current frequency of the CPU clock is set to the FPEFEQ parameter (general register

R4). The settable range I

φ of the FPEFEQ parameter is 32 to 40 MHz.

When the frequency is set out of this range, an error is returned to the FPFR parameter of

the initialization program and initialization is not performed. For details on the frequency

setting, see the description in section 21.4.3 (2.1), Flash Programming/Erasing Frequency

Parameter (FPEFEQ: General Register R4 of CPU).

2. The start address in the user branch destination is set to the (FUBRA: CPU general register

R5) parameter.

When the user branch processing is not required, 0 must be set to FUBRA.

When the user branch is executed, the branch destination is executed in flash memory other

than the one that is to be programmed. The area of the on-chip program that is downloaded

cannot be set.

The program processing must be returned from the user branch processing by the RTS

instruction.

See the description in section 21.4.3 (2.2), Flash User Branch Address Setting Parameter

(FUBRA: General Register R5 of CPU).

(2.7) Initialization

When a programming program is downloaded, the initialization program is also downloaded to

on-chip RAM. There is an entry point of the initialization program in the area from (download

start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed

by using the following steps.

MOV.L

#DLTOP+32,R1

; Set entry address to R1

JSR

@R1

; Call initialization routine

NOP

1. The general registers other than R0 are saved in the initialization program.

2. R0 is a return value of the FPFR parameter.

3. Since the stack area is used in the initialization program, a stack area of 256 bytes or more

must be reserved in RAM.

4. Interrupts can be accepted during the execution of the initialization program. However, the

program storage area and stack area in on-chip RAM and register values must not be

destroyed.

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