R5F72115D160FPV datasheet(950/1228 Pages) RENESAS

950 / 1228 page

Section 21 Flash Memory

Rev. 2.00 May. 08, 2008 Page 926 of 1200

REJ09B0344-0200

(2)

Programming Procedure in User Program Mode

The procedures for download, initialization, and programming are shown in figure 21.11.

Select on-chip program

to be downloaded and

set download destination

by FTDAR

Set FKEY to H'A5

Set internal clock ratio by

frequency control register

(FRQCR) to 4: 4: 4

After clearing VBR,

set SCO to 1 and

execute download

DPFR=0?

Yes

Download error processing

Set the FPEFEQ and

FUBRA parameters

Initialization

JSR FTDAR setting+32

Yes

End programming

procedure program

FPFR=0?

Initialization error processing

Clear FKEY to 0

Set parameter to R4 and

R5 (FMPAR and FMPDR)

Programming

JSR FTDAR setting+16

Yes

FPFR=0?

Clear FKEY and

programming

error processing

Yes

Required data

programming is

completed?

Set FKEY to H'5A

Clear FKEY to 0

(2.1)

(2.2)

(2.4)

(2.5)

(2.6)

(2.7)

(2.8)

(2.9)

(2.10)

(2.11)

(2.12)

(2.13)

(2.14)

(2.3)

Start programming

procedure program

Figure 21.11 Programming Procedure

The details of the programming procedure are described below. The procedure program must be

executed in an area other than the flash memory to be programmed. Especially the part where the

SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM. Specify 4:4:4

as the frequency division ratios of an internal clock (I

φ), a bus clock (Bφ), and a peripheral clock

φ) through the frequency control register (FRQCR).

The area that can be executed in the steps of the user procedure program (on-chip RAM, user

MAT, and external space) is shown in section 21.8.2, Areas for Storage of the Procedural Program

and Data for Programming.

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