H8S2245 datasheet(410/818 Pages) RENESAS

410 / 818 page

Section 10 8-Bit Timers

Rev.3.00 Mar. 26, 2007 Page 368 of 772

REJ09B0355-0300

10.2.4

Time Control Registers 0 and 1 (TCR0, TCR1)

CMIEB

R/W

CMIEA

R/W

OVIE

R/W

CCLR1

R/W

CCLR0

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

R/W

TCR0 and TCR1 are 8-bit readable/writable registers that select the clock source and the time at

which TCNT is cleared, and enable interrupts.

TCR0 and TCR1 are each initialized to H'00 by a reset and in hardware standby mode.

For details of this timing, see section 10.3, Operation.

Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt

requests (CMIB) are enabled or disabled when the CMFB flag of TCSR is set to 1.

Bit 7

CMIEB

Description

CMFB interrupt requests (CMIB) are disabled

(Initial value)

CMFB interrupt requests (CMIB) are enabled

Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt

requests (CMIA) are enabled or disabled when the CMFA flag of TCSR is set to 1.

Bit 6

CMIEA

Description

CMFA interrupt requests (CMIA) are disabled

(Initial value)

CMFA interrupt requests (CMIA) are enabled

Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests

(OVI) are enabled or disabled when the OVF flag of TCSR is set to 1.

Bit 5

OVIE

Description

OVF interrupt requests (OVI) are disabled

(Initial value)

OVF interrupt requests (OVI) are enabled

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