H8S2245 datasheet(411/818 Pages) RENESAS

411 / 818 page

Section 10 8-Bit Timers

Rev.3.00 Mar. 26, 2007 Page 369 of 772

REJ09B0355-0300

Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by

which TCNT is cleared: by compare match A or B, or by an external reset input.

Bit 4

Bit 3

CCLR1

CCLR0

Description

Clear is disabled

(Initial value)

Clear by compare match A

Clear by compare match B

Clear by rising edge of external reset input

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to

TCNT is an internal or external clock.

Three internal clocks can be selected, all divided from the system clock (

φ): φ/8, φ/64, and φ/8192.

The falling edge of the selected internal clock triggers the count.

When use of an external clock is selected, three types of count can be selected: at the rising edge,

the falling edge, and both rising and falling edges.

Some functions differ between channel 0 and channel 1.

Bit 2

Bit 1

Bit 0

CKS2

CKS1

CKS0

Description

Clock input disabled

(Initial value)

Internal clock, counted at falling edge of

φ/8

Internal clock, counted at falling edge of

φ/64

Internal clock, counted at falling edge of

φ/8192

For channel 0: count at TCNT1 overflow signal*

For channel 1: count at TCNT0 compare match A*

External clock, counted at rising edge

External clock, counted at falling edge

External clock, counted at both rising and falling edges

Note:

If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the

TCNT0 compare match signal, no incrementing clock is generated. Do not use this

setting.

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