H8S2245 datasheet(412/818 Pages) RENESAS

412 / 818 page

Section 10 8-Bit Timers

Rev.3.00 Mar. 26, 2007 Page 370 of 772

REJ09B0355-0300

10.2.5

Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1)

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

ADTE

R/W

OS3

R/W

OS0

R/W

OS2

R/W

OS1

R/W

Bit

Initial value

R/W

Note: * Only 0 can be written to bits 7 to 5, to clear these flags.

CMFB

R/(W)*

CMFA

R/(W)*

OVF

R/(W)*

—

OS3

R/W

OS0

R/W

OS2

R/W

OS1

R/W

Bit

Initial value

R/W

TCSR0

TCSR1

TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and

control compare match output.

TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode.

Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and

TCORB match.

Bit 7

CMFB

Description

[Clearing conditions]

(Initial value)

• Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB

• When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 with

the transfer counter not being 0

[Setting condition]

Set when TCNT matches TCORB

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