H8SLASH3021 datasheet(388/712 Pages) RENESAS

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11. Serial Communication Interface

Rev.2.00 Mar. 22, 2007 Page 364 of 684

REJ09B0352-0200

Clock: An internal clock generated by the on-chip baud rate generator or an external clock input

from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected

by the C/

A bit in SMR and bits CKE1 and CKE0 in SCR. See table 11.9.

When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 11.3 so that

the rising edge of the clock occurs at the center of each transmit data bit.

D0D1D2D3D4D5D6D7

0/1

1 frame

Figure 11.3 Phase Relationship between Output Clock and Serial Data

(Asynchronous Mode)

Transmitting and Receiving Data

SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE

bits to 0 in SCR, then initialize the SCI as follows.

When changing the communication mode or format, always clear the TE and RE bits to 0 before

following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes

TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and

RDR, which retain their previous contents.

When an external clock is used, the clock should not be stopped during initialization or subsequent

operation. SCI operation becomes unreliable if the clock is stopped.

Figure 11.4 shows a sample flowchart for initializing the SCI.

H8/3021 Datasheet(PDF) 388 Page - Renesas Technology Corp