H8SLASH3021 datasheet(20/712 Pages) RENESAS

20 / 712 page

Rev.2.00 Mar. 22, 2007 Page xx of xxiv

REJ09B0352-0200

12.4

Usage Note........................................................................................................................ 416

Section 13 A/D Converter................................................................................................. 419

13.1

Overview........................................................................................................................... 419

13.1.1 Features................................................................................................................ 419

13.1.2 Block Diagram..................................................................................................... 420

13.1.3 Pin Configuration................................................................................................. 421

13.1.4 Register Configuration......................................................................................... 422

13.2

Register Descriptions ........................................................................................................ 423

13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 423

13.2.2 A/D Control/Status Register (ADCSR) ............................................................... 424

13.2.3 A/D Control Register (ADCR) ............................................................................ 427

13.3

CPU Interface.................................................................................................................... 428

13.4

Operation .......................................................................................................................... 429

13.4.1 Single Mode (SCAN = 0) .................................................................................... 429

13.4.2 Scan Mode (SCAN = 1)....................................................................................... 431

13.4.3 Input Sampling and A/D Conversion Time ......................................................... 433

13.4.4 External Trigger Input Timing............................................................................. 434

13.5

Interrupts ........................................................................................................................... 435

13.6

Usage Notes ...................................................................................................................... 435

Section 14 RAM .................................................................................................................. 441

14.1

Overview........................................................................................................................... 441

14.1.1 Block Diagram..................................................................................................... 442

14.1.2 Register Configuration......................................................................................... 442

14.2

System Control Register (SYSCR) ................................................................................... 443

14.3

Operation .......................................................................................................................... 444

Section 15 ROM .................................................................................................................. 445

15.1

Features ............................................................................................................................. 445

15.2

Overview........................................................................................................................... 446

15.2.1 Block Diagram..................................................................................................... 446

15.2.2 Mode Transitions ................................................................................................. 447

15.2.3 On-Board Programming Modes........................................................................... 449

15.2.4 Flash Memory Emulation in RAM ...................................................................... 451

15.2.5 Differences between Boot Mode and User Program Mode ................................. 452

15.2.6 Block Configuration ............................................................................................ 453

15.3

Pin Configuration.............................................................................................................. 454

15.4

Register Configuration...................................................................................................... 454

15.5

Register Descriptions ........................................................................................................ 455

15.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 455

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