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H8/3021 Datasheet(PDF) 86 Page - Renesas Technology Corp

Part # H8/3021
Description  16-Bit Single-Chip Microcomputer
PDF  712 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8/3021 Datasheet(HTML) 86 Page - Renesas Technology Corp

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3. MCU Operating Modes
Rev.2.00 Mar. 22, 2007 Page 62 of 684
REJ09B0352-0200
3.4
Operating Mode Descriptions
3.4.1
Mode 1
Ports 1, 2, and 5 function as address pins A
19 to A0, permitting access to a maximum 1-Mbyte
address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.2
Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A
23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to
all areas. A
23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register
(BRCR). (In this mode A
20 is always used for address output.)
3.4.3
Mode 5
Ports 1, 2, and 5 can function as address pins A
19 to A0, permitting access to a maximum 1-Mbyte
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The address bus width can be selected freely by setting DDR of ports 1, 2, and 5. The initial
bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.4
Mode 6
Ports 1, 2, and 5, and port A (PA
7 to PA4) function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space, but following a reset these pins, except for A
20, are input ports.
To use ports 1, 2, and 5 as address bus pins A
19 to A0, the corresponding bits in their data direction
registers (P1DDR, P2DDR, and P5DDR) must be set to 1 to select output mode. A
23 to A21 are
enabled by writing 0 to bits 7 to 5 in the address control register (ADRCR). The address bus
width can be selected freely (excluding A
20) by setting DDR of ports 1, 2, and 5, and ADRCR.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.5
Mode 7
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. All I/O ports are available.
Note: The H8/3022 Group cannot be used in mode 2 and 4.



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