H8SLASH3021 datasheet(26/712 Pages) RENESAS

26 / 712 page

1. Overview

Rev.2.00 Mar. 22, 2007 Page 2 of 684

REJ09B0352-0200

Table 1.1

Features

Feature

Description

CPU

Upward-compatible with the H8/300 CPU at the object-code level

General-register machine

• Sixteen 16-bit general registers

(also useable as sixteen 8-bit registers or eight 32-bit registers)

High-speed operation

• Maximum clock rate: 18 MHz

• Add/subtract: 111 ns

• Multiply/divide: 778 ns

Two CPU operating modes

• Normal mode (64-kbyte address space)*

• Advanced mode (16-Mbyte address space)

Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

• Bit manipulation instructions with register-indirect specification of bit

positions

Memory

H8/3022

• ROM: 256 kbytes

• RAM: 8 kbytes

H8/3021

• ROM: 192 kbytes

• RAM: 8 kbytes

H8/3020

• ROM: 128 kbytes

• RAM: 4 kbytes

• Five external interrupt pins: NMI,

IRQ

0, IRQ1, IRQ4, IRQ5

Interrupt

controller

• 25 internal interrupts

• Three selectable interrupt priority levels

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